Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
Currently, circuits are designed for configuration in PLDs using either a behavioral language, such as C, Handel-C, and the like, or a hardware description language (HDL), such as the very high speed integrated circuit hardware description language (VHDL), VERILOG, and the like. In either case, a circuit designer must explicitly specify memory architectures for the circuit design (i.e., the allocation and partitioning of data over distributed memories). A circuit designer must spend significant design time for designing and coding the particular memory architecture for the design. Accordingly, there exists a need in the art for a more flexible memory management in circuit designs for integrated circuits, for example, PLDs.